DocumentCode :
3633236
Title :
FPGA-accelerated retinal vessel-tree extraction
Author :
A. Nieto;V. M. Brea;D. L. Vilarino
Author_Institution :
Departament of Electronics and Computer Science, University of Santiago de Compostela, E-15782, Spain
fYear :
2009
Firstpage :
485
Lastpage :
488
Abstract :
This work introduces an FPGA implementation for vesseltree extraction on retinal images. The retinal vessel-tree can be used in disease diagnoses, e.g. diabetes, or in person authentication. In such cases, a portable device with a high performance may be a need. The FPGA implementation discussed here, although application-oriented, features a fully programmable SIMD architecture, allowing for an efficient realization of low-level image processing algorithms. It is mapped onto a Spartan 3, amounting to 90 processing elements. The on-chip memory utilized was 1.4MB and stores 8 gray images of 144 × 160px. The working frequency is 53MHz, allowing for a 3 × 3 convolution in less than 110μs.
Keywords :
"Retina","Field programmable gate arrays","CMOS technology","Authentication","Algorithm design and analysis","Hardware","Image processing","Convolution","Active contours","Pixel"
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
ISSN :
1946-147X
Electronic_ISBN :
1946-1488
Type :
conf
DOI :
10.1109/FPL.2009.5272498
Filename :
5272498
Link To Document :
بازگشت