DocumentCode :
3633250
Title :
Metric-based transformations for self testable VLSI designs with high test concurrency
Author :
M. Vahidi;A. Orailoglu
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear :
1995
Firstpage :
136
Lastpage :
141
Abstract :
We propose an approach for improving the testability of a design under BIST methodology through behavioral restructuring. Our results show that the proposed transformations help reduce the number of required test sessions.
Keywords :
"Automatic testing","Very large scale integration","Concurrent computing","Circuit testing","Costs","Built-in self-test","Design for testability","High level synthesis","Design methodology","Computer science"
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC ´95., European
Print_ISBN :
0-8186-7156-4
Type :
conf
DOI :
10.1109/EURDAC.1995.527399
Filename :
527399
Link To Document :
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