• DocumentCode
    3633528
  • Title

    Automatic synthesizable VHLD code generation from neural networks models using Matlab

  • Author

    Karol Gugala;Andrzej Rybarczyk

  • Author_Institution
    Computer Engineering, Faculty of Computing and Management, Pozna? University of Technology, Poland
  • fYear
    2009
  • fDate
    6/1/2009 12:00:00 AM
  • Firstpage
    238
  • Lastpage
    241
  • Abstract
    The purpose of this work was to implement automatic synthesizable VHLD code generation from neural networks models algorithm in Matlab. We present generation algorithm usage and structure. VHDL models are generated with pipelined architecture, also there is hierarchical structure maintained in it. Example of generate model synthesis using Xilinx ISE 10.1 software result was presented.
  • Keywords
    "Network synthesis","Neural networks","Mathematical model","Neurons","Encoding","Integrated circuit modeling","Data structures","Transfer functions","Algorithm design and analysis","Integrated circuit synthesis"
  • Publisher
    ieee
  • Conference_Titel
    Mixed Design of Integrated Circuits & Systems, 2009. MIXDES ´09. MIXDES-16th International Conference
  • Print_ISBN
    978-1-4244-4798-5
  • Type

    conf

  • Filename
    5289500
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3633528