• DocumentCode
    3633836
  • Title

    SRAM yield enhancement with thin-BOX FD-SOI

  • Author

    Changhwan Shin;Min Hee Cho;Yasumasa Tsukamoto;Bich-Yen Nguyen;Borivoje Nikolic;Tsu-Jae King Liu

  • Author_Institution
    Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 94720 USA
  • fYear
    2009
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    The performance and yield of 6-T SRAM cells implemented in thin-BOX FD-SOI technology vs. bulk technology are compared via 3-dimensional (3D) atomistic process and device simulations and analytical modeling for SRAM yield estimation. Performance is enhanced due to the elimination of channel dopants, and variation due to gate-LER and RDF are suppressed, for FD-SOI technology. For the same cell area (∼0.07µm2), comparable SNM can be achieved with 30% higher write current, and SRAM yield is enhanced by ≫2 sigma.
  • Keywords
    "Random access memory","Resource description framework","Analytical models","Yield estimation","Very large scale integration","Electronic mail","Scanning electron microscopy","Resists","Electrodes","Computer simulation"
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2009 IEEE International
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4244-4256-0
  • Type

    conf

  • DOI
    10.1109/SOI.2009.5318780
  • Filename
    5318780
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3633836