SRAM cell design considerations for SOI technology

The performance and threshold-voltage variability of vertical SOI FinFETs are compared against those of planar fully depleted SOI MOSFETs with thin buried oxide, via three-dimensional device simulation with atomistic doping profiles and gate line-edge roughness, for the 22 nm CMOS technology node (25 nm gate length). Compact modeling is then used to estimate six-transistor SRAM cell performance metrics. Although FinFET technology offers superior performance, it is projected to have lower yield for comparable cell area, due to higher sensitivity to random and process-induced variations.