DocumentCode
3634256
Title
A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms
Author
Petr Fiser;David Toman
Author_Institution
Dept. of Comput. Sci., Czech Tech. Univ. in Prague, Prague, Czech Republic
fYear
2009
Firstpage
757
Lastpage
764
Abstract
We introduce a fast and efficient minimization method for functions described by many (up to millions) product terms. The algorithm is based on processing a newly proposed efficient representation of a set of product terms a ternary tree. A significant speedup of the look-up of the term operation is achieved, with respect to a standard tabular function representation. The minimization procedure is based on a fast application of basic Boolean operations upon a ternary tree. Minimization of incompletely specified functions is supported as well. The minimization method was tested on randomly generated large sums-of-products and collapsed ISCAS benchmark circuits. The performance of the proposed algorithm was compared with Espresso. A very advantageous application of the new minimization algorithm has been found if it is used for pre-processing a function having a large number of product terms, run prior to Espresso, the total minimization runtime is significantly reduced, whereas the result quality is not affected.
Keywords
"Minimization methods","Data structures","Boolean functions","Logic functions","Circuit synthesis","Network synthesis","Logic design","Circuit testing","Runtime","Built-in self-test"
Publisher
ieee
Conference_Titel
Digital System Design, Architectures, Methods and Tools, 2009. DSD ´09. 12th Euromicro Conference on
Print_ISBN
978-0-7695-3782-5
Type
conf
DOI
10.1109/DSD.2009.157
Filename
5350104
Link To Document