A vertically integrated 3D CMOS MAPS with in-pixel digital memory and delayed readout

In this paper, a novel 3D integrated rolling shutter mode binary pixel architecture, RSBPix (Rolling Shutter Binary PIXel), for charged particle tracking is presented. The analog part of the pixel consists of an n-well/p-substrate diode, a first amplification stage, a first double sampling circuitry, and a discriminator. The discriminator is made up of an offset-compensated multi-stage preamplifier and a latch. This approach allows to overcome process related mismatches of transistors and is compatible with low-voltage operation. During the integration phase, the pixels are selected row-by-row for amplification, discrimination and memorization of hits. This cycle is repeated sequentially during the arrival of bunches. Then, the memorized binary data of pixels corresponding to particle hits are readout slowly. A first prototype using RSBPix architecture has been designed in the Tezzaron & Chartered 3D-2Tier 130 nm CMOS process. The analog tier includes an array of 40×240 pixels divided in 9 sub-arrays with different diode sizes and transistor types. The pixel pitch is 20 μm, the chip size ~1.2 mm × 5.5 mm, and the power dissipation of the pixel ~120 μW. The pixel is readout in 80 ns. For test purpose, analog signals of 8 columns -out of 40 - can be observed directly, since their outputs are available without discriminators. Analog output buffers are also included on this tier. The digital tier includes a sequencer and output multiplexers for binary outputs. At the end of the readout chain, the digitized data are multiplexed on 8 outputs. Due to the limited design time, only a 1-bit memory was used for the pixel on this chip. All I/O pads are on the digital tier, and the analog tier is supplied by this one.