DocumentCode :
36349
Title :
A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling
Author :
Won-Hwa Shin ; Young-Hyun Jun ; Bai-Sun Kong
Author_Institution :
Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea
Volume :
60
Issue :
7
fYear :
2013
fDate :
Jul-13
Firstpage :
412
Lastpage :
416
Abstract :
In this brief, decision-feedback equalization (DFE) receiver for multidrop single-ended signaling is described. The proposed DFE receiver adopts a reference voltage having equalization information to remove channel intersymbol interference. It uses a smaller number of DFE tap elements than the conventional DFE receiver for the same level of equalization, resulting in reduced power consumption and silicon area, particularly for multi-input/output interface. The proposed DFE receiver was fabricated in a 0.13- μm CMOS process, whose evaluation results indicate a reliable operation up to 3.40-Gb/s data rate with reduced power consumption.
Keywords :
CMOS integrated circuits; decision feedback equalisers; intersymbol interference; power consumption; radio receivers; telecommunication signalling; CMOS process; DFE receiver; DFE tap element; channel intersymbol interference; decision-feedback equalization; equalization information; equalized VREF; multidrop single-ended signaling; multiinpu/output interface; reduced power consumption; reference voltage; reliable operation; silicon area; size 0.13 mum; Decision-feedback equalization (DFE) receiver; dynamic random access memory (DRAM) interface; multidrop channel; single-ended signaling;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2013.2258271
Filename :
6508848
Link To Document :
بازگشت