T0: A Single-Chip Vector Microprocessor with Reconfigurable Pipelines

A Single-Chip Fixed-Point Vector Microprocessor Is Described. The Chip Contains A Mips-Ii Risc Core With A 1 Kb Instruction Cache, Dual Eight-Way Parallel Vector Arithmetic Pipelines, A 128-Bit Memory Interface, And An 8-Bit Serial Host Interface. Each Vector Arithmetic Pipeline Contains A Cascade Of Six Functional Units That Can Be Dynamically Reconfigured By Each Instruction. The Resulting Peak Performance Is 4.3 Billion 32-Bit Arithmetic Operations Per Second At A Clock Speed Of 45 MHz.