In-system jitter measurement using FPGA

The paper describes architecture, detailed implementation and measurement results of newly developed jitter measurement device. The device is implemented using a single FPGA. Probably the biggest benefit of the proposed method is that it requires no external components, just the FPGA. As such it can be implemented into an existing receiver with an FPGA without any changes to its hardware. The new jitter measurement block was implementer and tested on a real link. Comparison with jitter measurement using an oscilloscope is given to prove its reasonable performance. Compared to previously published jitter measurement methods the module is able to monitor high frequency jitter. It is also very efficient in terms of required hardware resources.