Systematic expression shearing in symbolic CMOS circuits analysis based on topology reduction

This paper proposes a novel approach to the exact symbolic analysis of analog electronic circuits. The new method is entirely topology oriented. The procedure introduces a new graph representation of exact transfer function called Topology Decision Diagram (TDD). Its construction is based on topological interpretation of network function factorization process. The method considers every factorized part of the function as a subcircuit. Each subsequent subcircuit is obtained by replacing a regular circuit element with a singular element, when a circuit parameter is taken to a limit of infinity or zero. The new algorithm significantly improves compactness of the generated circuit equations by introduction of static element ordering and dynamic reordering during the TDD construction. Experimental results confirm the efficiency of the method.