Speed/power performance of D-type flip-flops in a 0.13µm SiGe∶C HBT technology demonstrated by a 86 GHz static frequency divider

The design and measurement of a static frequency divider in a 0.13µm BiCMOS SiGe∶C technology is presented. This investigation serves to characterize the D flip-flops (on which the static frequency divider is based) in a 100 Gb/s half-rate look ahead decision feedback equalizer (DFE) for optical fiber communications. Measurement result shows that the divider is working up to an input frequency of 86GHz with power consumption as low as 96.25mW per latch. The presented static frequency divider has the highest Speed/Power ratio among the recently published static frequency dividers in SiGe∶C technology which work above 80 GHz and do not employ integrated single ended to differential transformer at the input which limits the static frequency divider functionality at low frequencies.