Memory consistency models for shared memory multiprocessors and DSM systems

The use of systems with multiple processors that support shared memory programming paradigm is rapidly increasing nowadays. Possible buffering, pipelining, and optimization of shared memory accesses, as well as the existence of multiple copies of shared variables in these systems, may cause specific implications that can not be understood just as an intuitive extension of an uniprocessor memory model. Therefore, the memory consistency model formally specifies the memory system behavior to be expected by the programmer. This paper reveals the essence of several memory consistency models: sequential, processor, weak, release (with eager and lazy implementation), and entry. It also provides definitions and a set of examples that underline differences between particular models. Results of several performance evaluation studies are also discussed.