• DocumentCode
    3636704
  • Title

    RAMP gold: An FPGA-based architecture simulator for multiprocessors

  • Author

    Zhangxi Tan;Andrew Waterman;Rimas Avizienis;Yunsup Lee;Henry Cook;David Patterson;Krste Asanovic´

  • Author_Institution
    The Parallel Computing Laboratory CS Division, EECS Department, University of California, Berkeley
  • fYear
    2010
  • Firstpage
    463
  • Lastpage
    468
  • Abstract
    We present RAMP Gold, an economical FPGA-based architecture simulator that allows rapid early design-space exploration of manycore systems. The RAMP Gold prototype is a high-throughput, cycle-accurate full-system simulator that runs on a single Xilinx Virtex-5 FPGA board, and which simulates a 64-core shared-memory target machine capable of booting real operating systems. To improve FPGA implementation efficiency, functionality and timing are modeled separately and host multithreading is used in both models. We evaluate the prototype´s performance using a modern parallel benchmark suite running on our manycore research operating system, achieving two orders of magnitude speedup compared to a widely-used software-based architecture simulator.
  • Keywords
    "Gold","Field programmable gate arrays","Computational modeling","Computer architecture","Timing","Virtual prototyping","Software prototyping","Computer simulation","Operating systems","Discrete event simulation"
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2010 47th ACM/IEEE
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-4244-6677-1
  • Type

    conf

  • Filename
    5523116