Test pattern generator modification method for BIST

This paper gives an overview of on chip testing method. The test pattern generator generates appropriate test patterns that provide a highest possible fault coverage. The goal is to minimize the test lengths through suitable selection of initial state of TPG, to minimize hardware overhead and achieve high fault coverage for a reasonable test length. For the circuits with hard-to-detect faults we propose a method for designing modified pattern generators with the feasibility to transform some of generated vectors that do not detect any faults into deterministic vectors. Instead of lengthening the test set with additional generation of pseudorandom test vectors, some of ineffective generated vectors can be transformed into deterministic ones. The results of the experiments were studied on ISCAS85 and ISCAS89 benchmark circuits