Application dependent FPGA testing method using compressed deterministic test vectors

Tests that exercise complete FPGA resources are often more time and memory consuming than application dependent tests due to the high number of reconfigurations required for complete test. Presented application dependent test does not require reconfiguration of the tested hardware, thus it preserves conditions that led to the erroneous behavior of the FPGA device. The test method saves time and memory requirements of the test by storing compressed test patterns into the internal structure of the FPGA. The patterns are obtained with the help of the improved COMPAS algorithm – compression system based on test pattern overlapping. The COMPAS requires unused scan chains for the test pattern decompression. This is well suited for nowadays FPGAs which contain high number of LUT based shift registers. The neighborhood of the tested circuit is dynamically reconfigured into TPG and ORA. The TPG contains compressed test patterns which allow fast test pattern decompression. The paper demonstrates efficiency of this approach on experimental results.