Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications

This paper proposes a new solution dealing with functional safety in safety critical applications, especially with concern to the second edition of the standard IEC 61508. Actually, this new edition defines quite stringent requirements for the on-chip redundancy, such that its use in FPGAs may be compromised. Based on a previous study, which presents an on-chip coarse grained mixed-signal Triple Modular Redundancy architecture in FPGAs, this paper proposes a method to implement on-chip redundancy in FPGAs which complies with the new edition of the standard. Firstly, the paper will discuss the standard, thereafter the rules and constraints for the implementation of the on-chip redundancy, and finally it will evaluate the compliance of the method and suggest some improvements. The paper shows that the use of on-chip redundancy for FPGAs is achievable.