Title :
System on chip verification strategy based on FDL mechanism
Author_Institution :
Institute of Electronics, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland
Abstract :
The paper deals with problem of the formal verification of complex electronic embedded systems. A new com-monsense strategy is proposed. The formal methodology of the inference engine modeling based on Fuzzy Default Logic is given. The multistage verification strategy as the platform dependent verification (PDV) toolset is defined. The methodology has been validated on examples on a prototype AMBA-based virtual SoC platform working with SystemVerilog verification procedures. The advantages of the presented methodology have been emphasized.
Keywords :
"Object oriented modeling","Formal verification","Generators","System-on-a-chip","Planning","Unified modeling language","Flow graphs"
Conference_Titel :
Signals and Electronic Systems (ICSES), 2010 International Conference on
Print_ISBN :
978-1-4244-5307-8
