A low-power area-efficient switching scheme for charge-sharing DACs in SAR ADCs

Analysis and experimental results for a new switching scheme and topology for charge sharing DACs used in successive approximation register (SAR) ADCs is presented. The characteristics of the SAR algorithm are exploited to develop a switching scheme that reduces the number of required unit capacitors by nearly an order of magnitude over conventional charge sharing DACs without the aid of any additional reference voltages. The proposed topology also enables a rail-to-rail voltage swing at the DAC output enabling a differential voltage input at the ADC of up to twice the supply voltage. An 8-bit SAR ADC using the proposed DAC is implemented in a 90nm CMOS process and consumes 700 nW at 0.7 V and 100 kS/s while occupying 0.0135 mm².