An extended CAD methodology for sizing low-power low-voltage OTA architectures in decananometric technologies

This paper presents an extended CAD tool compatible with decananometric technologies for sizing OTA architectures. This is based on an extension of the gm/I methodology which uses, as inputs, parameters directly extracted from foundry models and can hence be easily ported to different technologies. This tool was developed in order to fasten and automate design for each OTA architecture. From fixed power consumption, the gain (Av), gain-bandwidth product (GBW), and unity gain frequency (fT) are compared among the analyzed performances. Examples are given in a bulk CMOS 65nm technology.