Title :
On a FPGA implementation of BCH codes
Author :
L. Ionescu;C. Anton;I. Tutănescu;A. Mazăre;G. Şerban
Author_Institution :
Faculty of Electronics, Communications and Computers - University of Piteş
Abstract :
Our paper presents the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) encoder and decoder using a Field Programmable Gate Array (FPGA) reconfigurable chip. The solutions implemented on FPGA lead to a high calculation rate using parallelization. We implemented the BCH code in a 3s400FG456 FPGA. In this implementation we used 15 bits-size word code and the results show that the circuits work quite well.
Keywords :
"Field programmable gate arrays","Receivers","Transmitters","Polynomials"
Conference_Titel :
Internet Technology and Secured Transactions (ICITST), 2010 International Conference for
Print_ISBN :
978-1-4244-8862-9
