DocumentCode :
3640228
Title :
A 2-Gb/s 5.6-mW digital equalizer for a LOS/NLOS receiver in the 60GHz band
Author :
Ji-Hoon Park;Brian Richards;Borivoje Nikolic
Author_Institution :
Electrical Engineering and Computer Sciences, University of California at Berkeley
fYear :
2010
Firstpage :
1
Lastpage :
4
Abstract :
The wide unlicensed bandwidth of a 60GHz channel presents an attractive opportunity for high data rate and low power personal area networks (PANs). The use of single-carrier modulation is beneficial for efficient transmitter and receiver implementation. Equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions based on the IEEE WPAN standard. Power consumption is minimized by using parallelized distributed arithmetic (DA). A 2mm ×2mm test chip in 65nm CMOS implements a 6-tap feedforward and 32-tap feedback equalizer that consumes 5.6mW at 2.0Gb/s throughput.
Keywords :
"Decision feedback equalizers","Channel estimation","Receivers","Power demand","Finite impulse response filter","Throughput"
Publisher :
ieee
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Print_ISBN :
978-1-4244-8300-6
Type :
conf
DOI :
10.1109/ASSCC.2010.5716622
Filename :
5716622
Link To Document :
بازگشت