Improve the automatic clock gating insertion in ASIC synthesis process using optimal enable function selection

In modern ASIC industry power consumption is becoming one of the most important constrains during the development phase. In 130nm technology and older, major part of the power consumption is a dynamic power and dynamic power optimization is usually taking the most of the time planed for the power optimization. Effective implementation and efficient utilization of clock gating (CG) logic is a critical element for dynamic power optimization since the clock gating is a dominant technique in dynamic power reduction. This paper is exploring the tradeoffs in clock gating that result in the lowest overall power consumption and optimization time. We are presenting the technique needed to be used in the situation when automatic clock gating is not acceptable.