ASIP data plane processor for multi-standard Interleaving and De-Interleaving

The Multi-Protocol Multi-Band (MPMB) Software Defined Radio (SDR) devices require flexible as well as efficient physical layer (PHY) processing. We address an efficient implementation of flexible PHY for Interleaving and De-Interleaving operation through Application Specific Instruction Set Processors (ASIPs). We propose a multi-standard (802.11a, 802.16e/m) supporting Interleaver / De-Interleaver ASIP, satisfying the throughput requirements of all the data-rates in both of the standards. The modular software implementation also allows supporting future wireless standards (that use block Interleaving/De-Interleaving) with variable rates. The paper presents the architecture of a reconfigurable processor, and the customization of the instruction set and registers files specific for Interleaving and De-Interleaving. We also discuss the area overhead and techniques to reduce it. The key idea developed here is to perform efficient bit-manipulation operations, through customization of base Instruction Set Architecture (ISA). The application with custom ISA achieves performance gain compared to base ISA, ranging from 5.02 times (802.11a BPSK) to 35 times (802.16e/m 64 QAM) in Interleaving. The performance gain in De-Interleaving varies from 5.21 times (802.11a BPSK) to 31.51 times (802.16e/m 64 QAM). The gain increases with the Number of Coded Bits per Symbol (NCBPS), as number of cycles/bit-operation decreases rapidly owing to custom instructions.