Communication on the Fly for Hierarchical Systems of Chip Multi-processors

Systems based on many Chip Multi-Processor (CMP) modules interconnected by global networks constitute now a feasible solution, which brings back to life challenges of massively parallel systems. The paper presents new methods for data communication inside CMP modules and for inter-CMP-module data communication. Inside CMP modules data communication through shared variables is improved by the use of dynamic core switching between core clusters organized in a system of multi-level caches with data reads on the fly. At the level of global data communication between CMP modules a special network implements communication between CMP module external shared memories with simultaneous reads on the fly to L2 data caches and main memories of CMP modules. Programs are built following a macro data flow graph paradigm.