Title :
Muller C-elements based on minority-3 functions for ultra low voltage supplies
Author :
Hans Kristian Otnes Berge;Amir Hasanbegović;Snorre Aunet
Author_Institution :
Department of Informatics, University of Oslo, P.B. 1080 Blindern, 0316, Norway
fDate :
4/1/2011 12:00:00 AM
Abstract :
Multiobjective optimization taking area, power consumption and robustness into account was used to pick two implementations of the minority-3 function as building blocks to implement Muller C-elements. According to our simulations, the generally better among the two implementations was a 12 transistor implementation based on a 10 transistor minority-3 gate, when compared to a 24 transistor implementation based on 2-input nand, 2-input nor and invert functions. For room temperature and a supply voltage of 150 mV, the simulated delays for the 12T and 24T implementations were 16.2 μs and 18.5 μs, respectively. The mean static power consumption figures were for the same conditions 2.6 pW and 7.4 pW, for the 12T and 24T implementations respectively. Switching energy was also simulated for a 150 mV supply voltage. The switching energy for the 12T version of the Muller C-element was almost 44% lower compared to the 24T implementation. We also report delay, power and energy for a supply voltage of 300 mV.
Keywords :
"Logic gates","Delay","Transistors","Power demand","Robustness","Optimization","Monte Carlo methods"
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Print_ISBN :
978-1-4244-9755-3
DOI :
10.1109/DDECS.2011.5783079