DocumentCode
3641338
Title
Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks
Author
C. Bolchini;F. Salice;D. Sciuto
Author_Institution
Dipt. di Sci. dell´Inf., Milan Univ., Italy
fYear
1997
Firstpage
32
Lastpage
37
Abstract
A new methodology for designing Totally Self-Checking combinational circuits through the encoding of the primary outputs with the parity code is presented. The parity code requires that each fault modifies an odd number of outputs for providing its detection, that is, each fault has to be oddly observable. The proposed methodology for fulfilling such a constraint consists of a post-synthesis modification of fault observability through either the introduction of an auxiliary output for the examined network node or the replication of the investigated node. A cost evaluation function allows us to select the most convenient solution in terms of overhead and the final 100% TSC circuit.
Keywords
"Intelligent networks","Circuit faults","Observability","Circuit synthesis","Combinational circuits","Encoding","Electrical fault detection","Fault detection","Circuit testing","Built-in self-test"
Publisher
ieee
Conference_Titel
VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on
ISSN
1066-1395
Print_ISBN
0-8186-7904-2
Type
conf
DOI
10.1109/GLSV.1997.580407
Filename
580407
Link To Document