Title :
3.3 V, novel circuit techniques for a 2.8-million-transistor BiCMOS RISC processor
Author :
F. Murabayashi;T. Yamauchi;M. Iwamura;T. Hotta;Y. Kobayashi;T. Nakano;K. Mori;T. Shimizu;R. Satomura;S. Mitani;K. Shiozawa;N. Kitamura;A. Yamagiwa;T. Hayashi
Author_Institution :
Hitachi Ltd., Ibaraki, Japan
Abstract :
3.3-V, high-speed circuit techniques, including a 0.6-ns single-ended common-base sense circuit, a 0.5-ns 22-b comparator circuit, and a 0.7-ns 3-input adder circuit, are applied to a 2.8-million-transistor RISC (reduced instruction set computer) microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS 3.3-V 4-metal-layer technology. The chip includes a 240-MFLOPS (million floating point operations per second) double-precision floating-point unit and a 24-kByte cache, and dissipates 17 W at 120 MHz.
Keywords :
"BiCMOS integrated circuits","Reduced instruction set computing","Bipolar transistors","Microprocessors","Integrated circuit noise","Energy consumption","Low voltage","MOSFETs","Registers","Logic circuits"
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590697
