FPGA implementation of multiple hardware watchdog timers for enhancing real-time systems security

In this work, we deal with securing the real-time systems by providing them with additional hardware watchdog timers. This paper proposes the basic concept of the multiple hardware watchdog timers system and describes the proposed architecture of the system providing 256 hardware watchdog timers. It deals with the particular implementation of the system in the FPGA programmable device. The results show that the developed system has a promising potential for enhancing the security of real-time systems and that the proposed architecture is suitable to be implemented in reasonably small programmable devices.