A chopper stabilized low-power differential ΔΣ ADC

This paper presents a differential SC second-order single-bit ΔΣ analog-to-digital converter (ADC). The converter has nominal conversion rate of 100 kS/s with OSR of 1000. Differential converter topology is used. This leads to lower second order harmonic and lower offset voltage compared to single ended topology. Together with SC implementation, the differential converter also makes it possible to use high impedance common mode reference voltages for low power operation. Chopper stabilization has been used to decrease offset and low frequency noise. The converter is designed and will be implemented in a 0.35 μm CMOS process with a total active area of 0.24 mm². Typically, it consumes 60 μA from a 3.3 V supply.