A high throughput MQ arithmetic encoder implementation for JPEG2000

In this paper, a high speed pipelined architecture with pipeline scheduler is presented for the JPEG2000 arithmetic encoder. The new design has removed the need for the additional hardware units for the procedures of the encoding process with suitably controlling the pipeline stages. The proposed system is described in Verilog HDL and targeted for the Xilinx Virtex-5 FPGA family. Results of the timing analysis showed that designed architecture is able to achieve 132 Msymbols/sec throughput.