Title :
A 1.1 GOPS/mW FPGA chip with hierarchical interconnect fabric
Author :
Cheng C. Wang;Fang-Li Yuan;Henry Chen;Dejan Markovic
Author_Institution :
Electrical Engineering Department, University of California, Los Angeles, USA
fDate :
6/1/2011 12:00:00 AM
Abstract :
A 2048 look-up-table FPGA with a radix-2 hierarchical interconnect network is realized in 3.94mm2 in 65-nm CMOS. It has an interconnect-to-logic area ratio of 1:1, which is a 3-4x reduction from modern FPGAs while allowing up to 100% resource utilization. As a proof of concept, it is designed with standard cells, achieving 16.4 GOPS/mm2 at 370MHz. Peak energy efficiency of 1.1 GOPS/mW is measured at 0.5V.
Keywords :
"Table lookup","Field programmable gate arrays","Digital signal processing","Routing","Integrated circuit interconnections","Logic gates","Delay"
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Print_ISBN :
978-1-61284-175-5
Electronic_ISBN :
2158-5636
