A Markov Performance Model for Buffered Protocol Design

Simulators play an important role in the design of VLSI circuits, but they require a large investment of time and effort. In this work we present a high-level, Markov model of a protocol, and we show how the best performing design can be selected without the need for simulation. Novel is the way we model the combinational logic and buffers as separate components. We compute the power consumed by each component, as well as the area complexity and data throughput. As a case study, we formally model the industrial protocol AMBA, and generate 84 designs that fulfil certain correctness requirements. We predict the performance and area complexity of every design, and we compare our predictions with the results from simulation. A fidelity and linear regression analysis is used to compute the correlation between the predictions and simulations. We also consider the competing goals of low-power and high-throughput, and how to select a design that offers an optimal compromise.