Input synchronization in low power CMOS arithmetic circuit design

Power dissipation in static CMOS circuits can be directly related to the signal transition activity of the circuit. Spurious, unwanted, transition activity can account for a large percentage of the overall transition activity. One cause of spurious activity is relative skew in the arrival time of asynchronous input signals. We measure the effects of input signal arrival skew on a typical CMOS full adder cell, on an 8-bit ripple carry, and on small partial product reduction arrays. We use three-state buffers to synchronize the inputs to these circuits and examine the trade-off.