On using 1-out-of-n codes for (p,q) counter implementations

A new approach for implementing (p,q) counters is introduced, using 1-out-of-n code modules. The circuits were implemented in 1.2 /spl mu/m CMOS technology, and simulated using HSpice to measure the cost, delay, and average power consumption. Through simulation, the new method is shown to yield an average 19% reduction in critical delay, and an average 30% reduction in average power consumption, with the tradeoff of a 38% increase in average cost.