Analysis of operation of ring LFSR used for testing of unidirectional interleaved interconnections

The paper presents analysis of operation of a specific ring LFSR register that can be used to test a network of n interleaved interconnections between modules of digital circuits. This register is a distinctive option of the already known BIST structure referred to as CSTP. When the test is carried out for unidirectional interconnections, the CSTP becomes a linear register and the lines under test make up feedback lines of that register. Due to the fact that layout of these lines looks like the `X´ letter that register is referred to as the XR-LFSR. The fault-free XR-LFSR can be reflected by an automaton with the G₀ cyclic state diagram and each physical defect f transforms that G₀ state diagram into another state diagram G_f ≠ G₀. To verify its efficiency for detection of faults the method of state diagram identification was applied. The same authors in previous studies dedicated to bus-type connections observed that the sequence of m states of G₀ state diagram, where m >; 2n and n >; 16, is sufficient to detect a substantial number of static and delay faults for such buses. The present paper comprises the observation that any randomly selected state of the state diagram for the XR-LFSR belongs, with a pretty high level of probability, exceeding 70%, to the cycle with the maximum length c_max. It was also spotted that for n>;16 more than 98,4% of all structures lead to sufficiently long cycles c_max >; 1000. The both observations confirmed usefulness of XR-LFSRs for testing of unidirectional connections.