Title :
Junction vertical slit field-effect transistor (JVeSFET) - compact DC model
Author :
Andrzej Pfitzner;Michał Staniewski;Michał Strzyga
Author_Institution :
Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland
fDate :
6/1/2011 12:00:00 AM
Abstract :
The VeSTIC technology proposed by Maly seems to be very attractive for manufacturing of mixed analogue/digital circuits of highly regular layout in nanoscale. First results of a feasibility study of a new JFET structure designed in the VeSTIC 3D geometry JVeSFETs are very promising and indicate good electrical properties. A preliminary compact model for circuit simulation has been presented in this paper.
Keywords :
"Numerical models","Logic gates","Mathematical model","Junctions","Threshold voltage","Semiconductor process modeling","Doping"
Conference_Titel :
Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference
Print_ISBN :
978-1-4577-0304-1
