Soft Error Recovery Technique for Multiprocessor SOPC

SRAM-based FPGA devices are becoming a suitable platform for implementing modern Systems On Programmable Chip (SOPC) due to their high reconfigurability, low cost and availability. The high performance SOPCs are often powered by multiple embedded microprocessors. FPGA devices are susceptible to radiation which causes soft-errors in their configuration memory. This paper proposes a soft error recovery technique for FPGA SOPC with multiple processors. The recovery algorithm runs on one of the embedded microprocessors at a time. The algorithm checks the configuration memory of the FPGA through the internal configuration access port and repairs a faulty configuration bit through partial reconfiguration. The technique also includes an extended recovery procedure where, upon the failure of the processor that runs the recovery algorithm, the error is recovered by another working processor. The proposed error recovery technique was verified by a case study and a fault emulation experiment.