Title :
BIST for SI sigma-delta analogue front end
Author :
P. Simek;V. Musil
Author_Institution :
Tech. Univ. of Brno, Czech Republic
Abstract :
A design methodology for built-in self test of switched-current (SI) oversampling sigma-delta analogue front ends is presented. The self-testing scheme enables to convert a sigma-delta modulator to form a delay line and perform self-testing without disconnection of feedback loops. Simulations of structural faults show high fault coverage for the proposed method. An analysis for more subtle designs has been made.
Keywords :
"Built-in self-test","Delta-sigma modulation","Circuit testing","Circuit faults","Automatic testing","Circuit simulation","Delay lines","Design methodology","Feedback loop","CMOS process"
Conference_Titel :
Circuits and Systems, 1997. ISCAS ´97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.612889
