Address generation unit as accelerator block in DSP

A wide variety of arithmetic intensive and scientific computing applications are characterized by a large number of data access. Such applications contain complex offset address manipulations. For most target digital signal processing (DSP) architectures, these memory-intensive applications present significant bottlenecks for system designs in term of memory bandwidth and memory access latencies, which can result in poor utilization of DSP computational logic. These time and space techniques require the design of optimized address generator units (AGUs) capable to deal with higher issue and execution rates, larger number of memory references, and demanding memory-bandwidth requirements. In this paper we described an efficient hardware AGU intended for fast generating memory addresses in 2D and 1D organized data memory embedded into a standalone accelerator processing block.