Realization of multistage FIR digital filters using pipelining\interleaving

A pipelining/interleaving (PI) technique is developed for efficient digital filtering. In this paper the method is applied on the multistage multichannel FIR filters with decimation, ie. interpolation in several steps. The implemented application and results of PI process for one of the effective implementation of these filters are shown in this paper. Filters are implemented using the field programmable gate array (FPGA) chips and also presents the results of this implementation.