FPGA realization of fully systolic and parallel architecture of Montgomery multipliers

Montgomery multipliers perform modular multiplication of two integers without trial division. They are often used in implementation of RSA algorithm which demands fast modular multiplication. This paper describes design and FPGA implementation of two architectures 16 bit Montgomery multipliers: fully systolic and parallel. Modules of multipliers are designed in VHDL with parameters easy to change and implemented in FPGA chip from Xilinx Virtex-4 family.