Real-time VP6 decoder optimization for MIPS based architectures

This paper describes the optimization of VP6 decoder for the MIPS based architectures. Programming languages C and inline assembler for the MIPS32 architecture were used. VP6 decoder with the main features is described, as well as MIPS processor and opportunities it offers. Profiling was performed for two data sets, and on the basis of these results optimization was performed using the vectorization. Finally, the execution time was measured for the decoder with data set, improvement for both test cases was obtained. Percentage of the consumption of the functions after optimization was calculated. The results were presented and analyzed.