DocumentCode :
3646164
Title :
Selective flexibility: Breaking the rigidity of datapath merging
Author :
Mirjana Stojilović;David Novo;Lazar Saranovac;Philip Brisk;Paolo Ienne
Author_Institution :
University of Belgrade, Institute Mihailo Pupin, Volgina 15, 11060, Serbia
fYear :
2012
fDate :
3/1/2012 12:00:00 AM
Firstpage :
1543
Lastpage :
1548
Abstract :
Hardware specialization is often the key to efficiency for programmable embedded systems, but comes at the expense of flexibility. This paper combines flexibility and efficiency in the design and synthesis of domain-specific datapaths. We merge all individual paths from the Data Flow Graphs (DFGs) of the target applications, leading to a minimal set of required resources; this set is organized into a column of physical operators and cloned, thus generating a domain-specific rectangular lattice. A bus-based FPGA-style interconnection network is then generated and dimensioned to meet the needs of the applications. Our results demonstrate that the lattice has good flexibility: DFGs that were not used as part of the datapath creation phase can be mapped onto it with high probability. Compared to an ASIC design of a single DFG, the speed of our domain-specific coarse-grained reconfigurable datapath is degraded by a factor up to 2×, compared to 3-4× for an FPGA; similarly, our lattice is up to 10× larger than an ASIC, compared to 20-40× for an FPGA. We estimate that our array is up to 6× larger than an ASIC accelerator, which is synthesized using datapath merging and has limited or null generality.
Keywords :
"Application specific integrated circuits","Merging","Field programmable gate arrays","Arrays","Delay","Routing","Educational institutions"
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
ISSN :
1530-1591
Print_ISBN :
978-1-4577-2145-8
Type :
conf
DOI :
10.1109/DATE.2012.6176718
Filename :
6176718
Link To Document :
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