Title :
Parallel digital image processor implemented in FPGA technology
Author :
Przemysław Brylski;Michał Strzelecki
Author_Institution :
Institute of Electronics, Technical University of Lodz, Wolczanska 211/215, 90-924 Lodz, Poland
Abstract :
In this paper a hardware implementation of parallel digital image processor in FPGA technology is presented. The circuit core is 16×16 array for image processing and analysis. Processor architecture and principle of operation is presented. Synthesis and implementation details are also described and discussed. The proposed processor was tested on labeling of binary images and obtained analysis results are presented and discussed.
Keywords :
"Field programmable gate arrays","Image segmentation","Microcontrollers","Digital images","Computer architecture","Clocks"
Conference_Titel :
Signal Processing Algorithms, Architectures, Arrangements, and Applications Conference Proceedings (SPA), 2011
Print_ISBN :
978-1-4577-1486-3
