A source-level dynamic analysis methodology and tool for high-level synthesis

Presents a novel source-level dynamic analysis methodology and tool for high-level synthesis (HLS). It not only enables HLS to offer source-level design debugging on ´synthesized´ RTL designs, but also allows the designer to analyze dynamic characteristics, such as resource utilization, power consumption, etc., at the algorithmic (source) level. This technology has been proven within the industry to be the critical element for successfully designing a microcontroller with over 300 instructions using Matisse, an interactive HLS system. Additionally, we demonstrate the use of this technology for architectural power optimization.