DocumentCode :
3646969
Title :
Current sensing completion detection in dual-rail asynchronous systems
Author :
Lukáš Nagy;Viera Stopjaková
Author_Institution :
Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
fYear :
2012
fDate :
4/1/2012 12:00:00 AM
Firstpage :
38
Lastpage :
41
Abstract :
This paper addresses a novel methodology of detecting the completion of computation process of the combinatorial block in asynchronous systems. Logic gates fabricated in CMOS technology draw electrical current in several orders of magnitude higher during the signal transitions than in the idle state. This fact can be used to separate the idle state and the computing activity. The paper presents the fundamental background of the completion methodology, detailed explanation of the sensing circuitry operation, achieved simulation results as well as the comparison to state-of-the-art methods of completion detection.
Keywords :
"Asynchronous circuits","Sensors","Power supplies","Logic gates","Synchronization","Latches","Standards"
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on
Print_ISBN :
978-1-4673-1187-8
Type :
conf
DOI :
10.1109/DDECS.2012.6219021
Filename :
6219021
Link To Document :
بازگشت