CMOS positive feedback latch structures for complementary signal edge alignment

This paper presents both fully complementary and symmetrical CMOS latch structures for complementary signal edge alignment, derived from NOR and NAND based CMOS latch implementations. Inherent edge misalignment, e.g. such caused by a technology imperfection or a design asymmetry, could decrease the robustness of a CMOS realisation of the latch structure. Therefore, latch topologies which employ positive feedback are introduced here in order to address this issue. The latches were designed and compared in the sense of the robustness by simulations using the TSMC 40nm CMOS technology device models.