Enhancing 6T SRAM cell stability by back gate biasing techniques for10nm SOI FinFETs under process and environmental variations

Process variations have shown to be critical for future Si-based bulk technologies. FinFETs have shown to be an alternative. In this work, we characterize the performance of the 6T SRAM cell by estimating read static noise margin and world line write margin for future FinFET-based 10nm technology. For simulation, we used HSPICE tool and SOI BSIM-CMG model card of 10nm FinFET previously developed by the University of Glasgow, Semiconductor Device Modeling Group. Process variations are based on ITRS predictions and they are modeled at the device level. On top of that, we also add environmental variations such as temperature and voltage. We also propose an effective procedure to apply the back-gate biasing technique for independent gate FinFET to the BSIM-CMG model card. As a specific example, we show how the RSNM of 6T SRAM cell can be improved by using back gate biasing techniques for independent gate FinFETs. First we show how WLMN is increased by reducing strength of pull up transistor with reverse back gate biasing of PU transistors. Then, we show how the RSNM can be increased by reducing the strength of access transistor by reverse back gate biasing of PG transistors. When combining these two techniques RSNM can be improved up to 25% without compromising cell write ability for any sample.