Autonomous test structures for synchronous sequential circuits

The paper shows an influence of a choice of autonomous testing structure on fault coverage in synchronous digital sequential circuit testing. In order to increase testability of sequential circuit during testing, its memory module usually undergoes a disconnection. At the time the testing structure gains access to no-primary output of the testing circuit. The circuit undergoes transformation into combinational circuit. A possibility of disconnection of a memory module results from including of multifunctional registers which execute a circuit memory function. It turns out that high fault coverage may often be gained without disconnection of the module. Thus, it is not necessary to apply such registers. Therefore the complexity of circuit is limited as far as a circuit area overhead for its application and additional mode control during its work are concerned. Nevertheless, it is not always possible. Even partial disconnection of memory modules during testing phase enables to increase fault coverage due to increasing circuit testability. Simulation studies carried out on a considerate amount of ISCAS´89 testing circuits set show rightness of introduced conception of sequential circuits testing without interference with its memory function. An important factor enabling suggested approach is an adequate choice of autonomous testing structure.